Advanced Packaging (CoWoS & SoIC) — Products

Engine-synthesised product landscape for Advanced Packaging (CoWoS & SoIC), ranked by trend signal across hiring, capital, orders, and discussion axes.

Last refresh: 2026-06-18.

CoWoS / CoWoS-L 2.5D Interposer Packaging — 2.5D advanced packaging service

Trend: · weak signal

Opportunity: CoWoS capacity is the binding constraint on AI accelerator supply: TSMC is ~doubling to ~75k wpm by end-2025, pushing reticle size to 5.5x in 2026 / 9x in 2027, and has raised prices 15-20% — yet B200 already needs 2.5x reticle CoWoS-L and NVIDIA still consumes ~60% of supply. Amkor + TSMC Peoria is the first attempt at non-Taiwan CoWoS but doesn't open until 2027-28, leaving Arizona-fabbed N3 die shipping back to Taiwan.

CoWoS is the single most-bottlenecked product in advanced packaging; TSMC is monopolist, NVIDIA is anchor customer, and Amkor is the only credible second source via the Peoria JV. Missing piece: any non-TSMC 2.5D capacity at scale before 2027.

Chiplets / UCIe Chiplet Interconnect — die-to-die interconnect & chiplet architecture

Trend: · weak signal

Opportunity: Chiplet decomposition is the structural alternative to monolithic scaling and is now mainstream at AMD (IOD+CCD) and Intel; UCIe speed bumps (post 9fc46a6c) signal the open-standard interconnect race is heating, with HN demand still asking basic 'what are chiplets and how are they packaged' (e735a1ee) — i.e., the abstraction is still being formed in public.

Chiplets are the architectural complement that makes 2.5D/3D advanced packaging economically necessary; AMD and Intel are the visible bettors, UCIe is the emerging standard, but no specific UCIe IP vendor surfaces in this evidence.