Advanced Packaging (CoWoS & SoIC) — Market

Verified claims and product-axis read for Advanced Packaging (CoWoS & SoIC). Every fact below is sourced; every product judgment traces back to underlying signals.

Verified facts

• SK Hynix's HBM order book is reportedly sold out through 2025 and largely committed through 2026. ↗ (other)
• Amkor's Q4 2024 advanced SiP packaging revenue rose ~24% YoY driven by Apple A18/M-series content gains. ↗ (financial)
• ASE acquired Infineon's facility (USG / SPIL?) and continues consolidating capacity to ramp advanced packaging output by ~40% YoY in 2025. _(historical_event)_
• Amkor's R&D spending was approximately $215M in 2024 (~3.4% of revenue), heavily weighted toward advanced packaging. ↗ (financial)
• SK Hynix HBM3e 12-Hi began mass production in September 2024, ahead of Samsung's first 12-Hi mass production target. ↗ (other)
• TSMC has reportedly raised CoWoS prices by ~15-20% for 2025 contracts in response to demand outstripping capacity. ↗ (other)
• SK Hynix and TSMC announced a joint HBM4 collaboration in April 2024 where TSMC fabs the HBM4 base die using N5/N12 logic process. ↗ _(historical_event)_
• TSMC Arizona Fab 2 (N3) is scheduled for production start in 2028 but no CoWoS capacity is co-located, requiring shipment back to Taiwan for packaging until Amkor Peoria opens. ↗ _(historical_event)_
• NVIDIA B200 uses 8 HBM3e stacks at 192GB total memory and ~8TB/s bandwidth, requiring 2.5x reticle CoWoS-L interposer. ↗ _(technical_spec)_
• AMD MI300X uses 8 HBM3 stacks at 192GB total with TSMC SoIC for compute-on-I/O 3D stacking. ↗ (other)

Top products (engine read)

CoWoS / CoWoS-L 2.5D Interposer Packaging — 2.5D advanced packaging service

Opportunity: CoWoS capacity is the binding constraint on AI accelerator supply: TSMC is ~doubling to ~75k wpm by end-2025, pushing reticle size to 5.5x in 2026 / 9x in 2027, and has raised prices 15-20% — yet B200 already needs 2.5x reticle CoWoS-L and NVIDIA still consumes ~60% of supply. Amkor + TSMC Peoria is the first attempt at non-Taiwan CoWoS but doesn't open until 2027-28, leaving Arizona-fabbed N3 die shipping back to Taiwan.

CoWoS is the single most-bottlenecked product in advanced packaging; TSMC is monopolist, NVIDIA is anchor customer, and Amkor is the only credible second source via the Peoria JV. Missing piece: any non-TSMC 2.5D capacity at scale before 2027.

Chiplets / UCIe Chiplet Interconnect — die-to-die interconnect & chiplet architecture

Opportunity: Chiplet decomposition is the structural alternative to monolithic scaling and is now mainstream at AMD (IOD+CCD) and Intel; UCIe speed bumps (post 9fc46a6c) signal the open-standard interconnect race is heating, with HN demand still asking basic 'what are chiplets and how are they packaged' (e735a1ee) — i.e., the abstraction is still being formed in public.

Chiplets are the architectural complement that makes 2.5D/3D advanced packaging economically necessary; AMD and Intel are the visible bettors, UCIe is the emerging standard, but no specific UCIe IP vendor surfaces in this evidence.

See the Products and Strategy modules for the full product list and forward-looking judgment.