AI ASICs — Silicon Commitment Radar

Six AI ASIC teams — AMD, Groq, Cerebras Systems, Tenstorrent, SambaNova Systems, and Rebellions — are all posting for physical design, place and route, and timing closure engineers in the same hiring window. That is not coincidence; it is a structural signal worth reading carefully if you are deciding where to move next.

The architecture thesis: AI compute at scale is no longer a monolithic die problem. Every team in this group is converging on 2.5D/3D chiplet architectures with HBM and UCIe interconnects — AMD, Cerebras, and Rebellions explicitly so — which means each shop must re-solve physical implementation from scratch on new process nodes and packaging stacks. Groq's LPU adds a separate constraint: a deterministic, compiler-first execution model that requires timing closure to be treated as a first-class design constraint, not a back-end cleanup step.

On capital deployment: AMD has simultaneously opened a new $5.0B unsecured revolving credit facility and expanded its commercial paper program from $3.0B to $5.5B. That is liquidity positioned for sustained silicon investment cycles, not opportunistic financing.

The scarce skill is physical design — specifically engineers who can handle advanced packaging co-design (HBM attachment, UCIe PHY placement, bump map optimization) alongside conventional PnR and timing closure. Advanced packaging ranks as the second-highest specialty cluster in active job postings across these teams, directly behind core PD. Engineers who hold both competencies are the rate-limiting resource in this build-out.

The distinction that matters for career decisions: these companies are staffing and ordering. That is different from being discussed.

Where is the tightest constraint you are seeing in production AI ASIC PD work — chiplet I/O co-design, HBM integration, or timing closure on advanced nodes?