CPO Is Shipping. The Skills Aren't.

Co-Packaged Optics Just Got a Shipping Date — and a Talent Problem

The inflection most optical engineers have been anticipating for half a decade arrived quietly: Broadcom's Tomahawk 6 ('Davisson'), a 102.4T-class switch ASIC with co-packaged silicon photonics, is shipping. NVIDIA has publicly endorsed CPO for AI GPU fabrics. That combination converts co-packaged optics from conference-room slide to procurement line item. The downstream effect: a narrow, specialized skill set is now in acute demand, and companies still treating CPO as a future concern are already behind on headcount.

Why CPO at 102.4T and Not Before

Front-panel pluggable transceivers hit a structural ceiling approaching 1.6T per port: SerDes signal integrity degrades over the PCB trace from switch ASIC to faceplate, and power per Gb/s rises faster than module density can compensate. The math stops working cleanly around 102.4T aggregate switch bandwidth — exactly the class Tomahawk 6 targets.

Co-packaged optics address this by moving the optical engine onto the same substrate as the switch ASIC, eliminating the lossy electrical trace. Power per Gb/s drops; aggregate I/O bandwidth scales. The tradeoff: this is no longer a module swapped in a data-center aisle. It is a new packaging and assembly discipline with its own yield curves, test vectors, and failure modes — none of which map cleanly onto pluggable transceiver expertise.

Astera Labs: The Hiring Tell

Among companies with disclosed job requisitions, Astera Labs provides the most granular signal of where CPO engineering effort is actually landing. Current or recent open roles include:

• Photonic packaging engineer — fiber-to-chip attach process, interposer co-design, assembly yield
• CPO test and optical validation engineer — system-level bring-up, link-margin measurement, jitter/BER characterization specific to co-packaged configurations
• PIC/EIC co-design engineer — photonic integrated circuit and electronic IC bring-up, electro-optic co-simulation, silicon-photonics process corners

These are not entry-level postings. The PIC/EIC title implies familiarity with silicon-photonics PDKs (TSMC SiPh, AIM Photonics, or equivalent), photonic schematic-to-layout, and electro-optic co-simulation — a skill combination residing in a narrow global talent pool. Astera Labs is also staffing 800G optical firmware and PAM4-DSP principals in parallel, signaling that CPO investment is running alongside capturing today's pluggable socket, not instead of it.

The Three Chokepoints Engineers Are Actually Solving

1. Photonic packaging yield. Coupling a single-mode fiber array to a photonic chip with sub-micron alignment tolerance, at volume, with assembly yield sufficient to underwrite a hyperscaler purchase order — this is the central unsolved production problem. Molex and Teramount are among the named attach-process vendors in industry discussion; their hiring and order flow is a leading indicator of when volume production is real versus pilot-line.

2. CPO test infrastructure. Traditional transceiver test fixtures plug into QSFP cages. A co-packaged module never leaves the switch chassis after assembly. That means optical bring-up, BER sweep, and reliability screening all happen at board or system level — requiring custom fixtures, automated optical alignment stages, and software stacks that largely do not yet exist as off-the-shelf products. Engineers who can design those fixtures, write measurement scripts, and define acceptance criteria are scarce and recognized as such in active headcount discussions.

3. Thermal co-design. Pluggable transceivers thermally decouple from the switch ASIC via the faceplate. Co-packaged optical engines sit on the same substrate as an ASIC dissipating hundreds of watts. Thermal simulation, heat-spreader co-design, and package-level thermal validation are now optical-engineer problems — a discipline boundary shift that most optical teams have not yet staffed for.

The Bear Case Is Still Live

Jensen Huang's public framing — that copper survives intra-rack longer than CPO advocates project — has not disappeared from industry debate. The engineering argument: direct-attach copper cables (DAC) and active copper cables (ACC) continue to improve their reach-versus-power curves, and at rack scale the latency delta versus optical is negligible. For GPU-to-GPU within a single rack or two, copper remains simpler, cheaper, and field-replaceable.

CPO's current addressable deployment is AI spine and inter-rack interconnect — a large TAM, but not every front-panel socket. Engineers evaluating the space should note that CPO talent compounds fastest at companies building for AI spine fabrics (hyperscaler build-to-spec or merchant silicon for those deployments). Intra-rack remains contested for at least another product generation.

Silicon Photonics: The Foundry Race Underneath

Every CPO engine is built on a silicon-photonics PIC. The foundry infrastructure to produce these PICs at data-center volume is still developing:

• TSMC is investing in a silicon-photonics process platform, providing the manufacturing anchor for several CPO roadmaps
• MACOM received CHIPS Act funding to expand InP (indium phosphide) laser capacity — InP is the dominant material for light sources inside PICs
• Marvell disclosed a 1 THz modulator, extending the per-lane bandwidth ceiling for future PIC generations

InP laser supply is separately flagged in community discussion as a near-term production gating factor. Engineers with InP epitaxy, laser characterization, or III-V integration backgrounds are in a narrow but high-leverage position relative to current demand.

Career Radar: Committed vs. Talking

The difference between companies committed to CPO and those still exploring is visible in job-function specificity. A posting for "optical engineer, AI infrastructure" signals exploration. A posting for "fiber-to-chip attach process engineer, photonic packaging yield" or "CPO test fixture architect" signals a product within one cycle of production.

Roles to watch as leading indicators across the supply chain:

• Fiber-to-chip attach / photonic packaging yield (assembly)
• CPO bring-up and optical validation (test)
• PIC/EIC co-design with silicon-photonics PDK experience (design)
• InP laser characterization / III-V process integration (materials)
• Thermal co-design for co-packaged assemblies (cross-disciplinary)

Broadcom committing Tomahawk 6 to volume and NVIDIA endorsing CPO for AI fabrics sets the demand signal. The companies staffing the above functions now are building the engineering base that production CPO requires. The ones still posting generic optical-engineer titles are not — and that gap will widen as 102.4T AI fabric deployments accelerate.